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M52S128168A-7.5BG 参数 Datasheet PDF下载

M52S128168A-7.5BG图片预览
型号: M52S128168A-7.5BG
PDF下载: 下载PDF文件 查看货源
内容描述: 1M ×16位×4银行同步DRAM [1M x 16 Bit x 4 Banks Synchronous DRAM]
分类和应用: 存储内存集成电路动态存储器
文件页数/大小: 47 页 / 1192 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
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ESMT  
Preliminary  
M52S128168A  
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)  
-7.5  
-10  
Parameter  
Symbol  
tCC  
Unit  
ns  
Note  
Min  
7.5  
12  
-
Max  
Min  
10  
Max  
CAS Latency =3  
CLK cycle time  
1000  
1000  
1
1
CAS Latency =2  
CAS Latency =3  
CAS Latency =2  
12  
6
9
7
CLK to valid  
output delay  
tSAC  
ns  
-
10  
Output data hold time  
CLK high pulse width  
CLK low pulse width  
Input setup time  
tOH  
tCH  
tCL  
2.5  
2.5  
2.5  
2
2.5  
3
ns  
ns  
ns  
ns  
ns  
ns  
2
3
3
3
3
2
3
tSS  
tSH  
tSLZ  
2.5  
1
Input hold time  
1
CLK to output in Low-Z  
1
1
CLK to output in CAS Latency =3  
Hi-Z  
6
9
7
tSHZ  
ns  
10  
CAS Latency =2  
*All AC parameters are measured from half to half.  
Note: 1.Parameters depend on programmed CAS latency.  
2.If clock rising time is longer than 1ns,(tr/2-0.5)ns should be added to the parameter.  
3.Assumed input rise and fall time (tr & tf)=1ns.  
If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr+ tf)/2-1]ns should be added to the  
parameter.  
Elite Semiconductor Memory Technology Inc.  
Publication Date: May. 2007  
Revision: 1.0 7/47  
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