ESMT
Preliminary
M52S128168A
AC OPERATING TEST CONDITIONS (VDD=2V ± 0.1V,TA= 0°C ~ 70°C )
Parameter Value
Unit
V
V
ns
V
Input levels (Vih/Vil)
0.9 x VDDQ / 0.2
0.5 x VDDQ
tr / tf = 1 / 1
0.5 x VDDQ
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
See Fig.2
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Version
-7.5
Parameter
Unit
Note
Symbol
-10
Row active to row active delay
tRRD(min)
15
15
20
ns
ns
1
1
tRCD(min)
20
RAS to CAS delay
Row precharge time
tRP(min)
tRAS(min)
15
48
20
50
ns
ns
1
1
Row active time
tRAS(max)
tRC(min)
100
us
-
1
@Operating
Row cycle time
63
90
ns
@Auto refresh
tRFC(min)
80
1
ns
1 , 5
2
Last data in to new col. Address delay
Last data in to row precharge
tCDL(min)
CLK
CLK
CLK
CLK
CLK
tRDL(min)
2
2
Last data in to burst stop
tBDL(min)
1
2
Col. Address to col. Address delay
Mode Register command to Active or Refresh Command
tCCD(min)
1
3
tMRD(min)
CAS latency=3
CAS latency=2
tBEF(max)
2
-
2
Number of valid output data
Refresh period(4,096 rows)
ea
4
6
1
ms
64
Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and
then rounding off to the next higher integer.
3. Minimum delay is required to complete write.
4. All parts allow every cycle column address change.
5. In case of row precharge interrupt, auto precharge and read burst stop.
The earliest a precharge command can be issued after a Read command without the loss of data is CL+BL-2 clocks
5. A new command may be given tRFC after self refresh exit.
6. A maximum of eight consecutive AUTO REFRESH commands (with tRFCmin) can be posted to any given SDRAM,and
the maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is
8x15.6μs.)
Elite Semiconductor Memory Technology Inc.
Publication Date: May. 2007
Revision: 1.0 6/47
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
