ESMT
Preliminary
M52S128168A
DC CHARACTERISTICS
Recommended operating condition unless otherwise noted，TA = 0 to 70°C
CAS
Latency
Version
Parameter
Symbol
Test Condition
Unit Note
-7.5
-10
Burst Length = 1
tRC ≥ tRC (min), tCC ≥ tCC (min), IOL= 0mA
Operating Current
(One Bank Active)
ICC1
65
60
mA
1
Precharge Standby
Current in power-down
mode
ICC2P
0.5
0.5
CKE ≤ VIL(max), tCC =15ns
mA
mA
ICC2PS
CKE ≤ VIL(max), CLK ≤ VIL(max), tCC = ∞
CKE ≥ VIH(min), CS ≥ VIH(min), tCC =10ns
10
5
mA
ICC2N
Precharge Standby
Current in non
power-down mode
Input signals are changed one time during 20ns
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable
mA
mA
ICC2NS
ICC3P
5
2
CKE ≤ VIL(max), tCC =15ns
Active Standby Current
in power-down mode
ICC3PS
CKE ≤ VIL(max), CLK ≤ VIL(max), tCC = ∞
CKE ≥ VIH(min), CS ≥ VIH(min), tCC=10ns
20
15
mA
ICC3N
Active Standby Current
in non power-down
mode
Input signals are changed one time during 20ns
CKE ≥ VIH (min), CLK ≤ VIL(max), tCC= ∞
Input signals are stable
mA
mA
ICC3NS
(One Bank Active)
IOL= 0mA, Page Burst
All Band Activated, tCCD = tCCD (min)
1
2
Operating Current
(Burst Mode)
70
60
ICC4
ICC5
Refresh Current
130
120
tRC ≥ tRC(min)
TCSR range
4 Banks
mA
°C
45
70
200
150
130
330
230
190
ICC6
CKE ≤ 0.2V
uA
uA
2 Bank
Self Refresh Current
1 Bank
Deep Power Down
Current
ICC7
CKE ≤ 0.2V
10
Note: 1.Measured with outputs open. Addresses are changed only one time during tCC(min).
2.Refresh period is 64ms. Addresses are changed only one time during tCC(min).
Elite Semiconductor Memory Technology Inc.
Publication Date: May. 2007
Revision: 1.0 5/47
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
