ESMT
Preliminary
M52S128168A
BA1BA0 A11 A10 A9 A8 A7
A6
DS
A5 A4
A3
0
A2 A1 A0 Address bus
PASR Extended Mode Register Set
1
0
0
0
0
0
0
0
A2-A0
000
WT=0
4Bank
001
2 Bank (BankA& BankB) or
(BA1=0)
1 Bank (BankA) or
PASR
010
(BA0=BA1=0)
011
100
101
111
R
R
R
R
A6-A5
00
01
10
11
Driver Strength
Full Strength
1/2 Strength
1/4 Strength
R
DS
Remark R : Reserved
EXTENDED MODE REGISTER SET (EMRS)
The extended mode register stores for selecting PASR;TCSR;DS. The extended mode register set must be done before any active
command after the power up sequence. The extended mode register is written by asserting low on CS,RAS,CAS,WE and high on
BA1,low on BA0(The SDRAM should be in all bank precharge with CKE already high prior to writing into the extended more
register). The state of address pins
A0~An in the same cycle as CS,RAS,CAS,WE going low is written in the extended mode register. Refer to the table for specific
codes.
The extended mode register can be changed by using the same command and clock cycle requirements during operations as long
as all banks are in the idle state. The default value extended mode register is defined as half driving strength and all banks
refreshed.
Elite Semiconductor Memory Technology Inc.
Publication Date: May. 2007
Revision: 1.0 10/47
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
