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M52D128168A-10BIG 参数 Datasheet PDF下载

M52D128168A-10BIG图片预览
型号: M52D128168A-10BIG
PDF下载: 下载PDF文件 查看货源
内容描述: 2M ×16位×4银行同步DRAM [2M x 16 Bit x 4 Banks Synchronous DRAM]
分类和应用: 动态存储器
文件页数/大小: 47 页 / 1134 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
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ESMT  
M52D128168A  
Operation Temperature Condition -40°C~85°C  
8. Burst Stop & Interrupted by Precharge  
1 ) W r i t e B u r s t S t o p ( B L = 8 )  
1 ) W r i t e in t e r r u p t e d b y p r e c h a r g e ( B L = 4 )  
C LK  
C L K  
* N o t e 3  
* N o t e 4  
CMD  
WR  
CM D  
W R  
D 0  
PR E  
ST OP  
t R DL  
DQ M  
DQ  
DQ M  
DQ  
M a sk  
D 0  
D 3  
D1  
M a sk  
D1  
D2  
D 4  
D5  
* N o t e 1  
t B DL  
2 ) R e a d B u r s t S t o p (B L = 4 )  
2 ) R e a d i n t e r r u p t e d b y p r e c h a r g e ( B L =4 )  
CL K  
CL K  
* N o t e 5  
C MD  
C M D  
R D  
PR E  
RD  
STO P  
Q0  
* N o t e 2  
DQ (C L2 )  
D Q( C L3 )  
Q1  
Q0  
* No t e 2  
D Q( C L 2 )  
D Q( CL 3 )  
Q0  
Q1  
Q1  
Q0  
Q2  
Q1  
Q3  
Q2  
Q3  
9. MRS  
1 ) M o d e R e g is t e r S e t  
C LK  
*N o t e 6  
C MD  
AC T  
PR E  
MRS  
t RP  
2 C L K  
*Note: 1. tBDL : 1 CLK ; Last data in to burst stop delay.  
Read or write burst stop command is valid at every burst length.  
2. Number of valid output data after burst stop : 1,2 for CAS latency = 2,3 respectiviely.  
3. Write burst is terminated. tRDL determinates the last data write.  
4. DQM asserted to prevent corruption of locations D2 and D3.  
5. Precharge can be issued here or earlier (satisfying tRAS min delay) with DQM.  
6. PRE : All banks precharge, if necessary.  
MRS can be issued only at all banks precharge state.  
Elite Semiconductor Memory Technology Inc.  
Publication Date: Sep. 2008  
Revision: 1.0 23/47  
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