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M52D128168A-10BIG 参数 Datasheet PDF下载

M52D128168A-10BIG图片预览
型号: M52D128168A-10BIG
PDF下载: 下载PDF文件 查看货源
内容描述: 2M ×16位×4银行同步DRAM [2M x 16 Bit x 4 Banks Synchronous DRAM]
分类和应用: 动态存储器
文件页数/大小: 47 页 / 1134 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
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ESMT  
M52D128168A  
Operation Temperature Condition -40°C~85°C  
6. Precharge  
1 ) N o r m a l W r i t e ( B L = 4 )  
2 ) N o r m a l R e a d ( B L = 4 )  
CLK  
C M D  
D Q  
CLK  
C M D  
PR E CL= 2  
PR E  
W R  
D0  
R D  
* N o t e 2  
Q3  
Q2  
DQ ( C L 2 )  
C M D  
Q0  
Q1  
Q0  
D3  
D1  
D2  
tR D L  
* N o t e 1  
CL = 3  
Q2  
PR E  
Q1  
* N o t e 2  
Q3  
DQ ( C L 3 )  
.
7. Auto Precharge  
1 ) N o r m a l W r i t e ( B L = 4 )  
2 ) N o r m a l R e a d ( B L = 4 )  
CLK  
CLK  
C M D  
C M D  
D Q  
W R  
R D  
DQ ( C L 2 )  
DQ ( C L 3 )  
D0  
D2  
D1  
D3  
D2  
D0  
D2  
D3  
D1  
D1  
D0  
tR D L ( m i n )  
D3  
* N o t e 3  
Auto Pr ech arge st ar t s  
* N o t e 3  
Auto Pr ech arge st art s  
*Note : 1. tRDL : Last data in to row precharge delay.  
2. Number of valid output data after row precharge : 1,2 for CAS Latency = 2,3 respectively.  
3. The row active command of the precharge bank can be issued after tRP from this point.  
The new read/write command of other activated bank can be issued from this point.  
At burst read/write with auto precharge, CAS interrupt of the same/another bank is illegal.  
Elite Semiconductor Memory Technology Inc.  
Publication Date: Sep. 2008  
Revision: 1.0 22/47  
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