M32L1632512A
Read & Write Cycle with Auto Precharge II @ Burst Length =4
11
12
13
15
17
19
1
2
3
9
10
14
16
18
0
4
5
6
7
8
C L O C K
C K E
H I G H
C S
R A S
C A S
R a
R b
C a
R a
C a
A D D R
C b
A10
A9
R a
R b
R a
W E
D SF
D Q M
DQ C L =2
Da1
Da1
Qa0
Qa1 Qb0 Qb1
D b3
Db2
Db2
Da0
Da0
Qa0
Qa1 Qb0 Qb1
D b3
W r ite wi th
Auot Pr echarge
( A- Bank )
Row Ac t i ve
(A -Ban k )
Rea d wit h
Auto Pr ec harg e
( A- Bank )
Prec harge
( B- Ban k )
Row A c t i v e
(A- Ban k )
Row A c t i v e
(B- Ban k )
Read without Auto
Pr ec har ge(B -Ban k )
Au toPreaharge
Star t Poin t
( A- Bank )
:D on' t C ar e
*Note : 1. When Read(Write) command with auto precharge is issued at A-Bank after A and B Bank activation.
- If Read(Write) command without auto precharge is issued at B-Bank before A Bank auto precharge starts, A Bank
auto precharge will start at the next cycle of B Bank read command input point.
- any command can not be issued at A Bank during RP after A Bank auto precharge starts.
t
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2001
Revision : 1.6 44/54
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
