M32L1632512A
Page Read Cycle at Different Bank @ Burst Length = 4
11
12
13
15
17
19
1
2
3
9
10
14
16
18
0
4
5
6
7
8
C L O C K
H I G H
C K E
* N o t e1 `
C S
R A S
*N o t e 2 `
C A S
R Aa
CAa R Bb
C Ac
CB d
A D D R
CBb
CA e
A10
A9
R Aa
R Bb
W E
D SF
LOW
D Q M
DQ C L= 2
QAa2 QAa3 QBb0
QAc 0 QAc 1 QBd0 QBd1 QAe0 QAe1
QBb1 QBb2 QBb3
QAa0
QAa1
QBb2
QBb3 QAc0
QAc 1 QBd0 QBd1 QAe0 QAe1
C L =
3
QAa0 QAa1 QAa2 QAa3 QBb0 QBb1
Read
Read
Read
(B - Ban k )
Read
(A- Ban k )
Pr echar ge
( A- B an k )
Row Ac t i ve
( A- B an k )
Ro w A c ti ve
( B- Ban k )
(A- Ban k )
(B- Ban k )
Read
(A- Ban k )
:D on' t C ar e
*Note : 1. CS can be don’t care when RAS , CAS and WE are high at the clock high going edge.
2. To interrupt a burst read by row precharge, both the read and the precharge banks must be the same.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2001
Revision : 1.6 40/54
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
