M32L1632512A
Read & Write Cycle with Auto Precharge @ Burst Length =4
11
12
13
15
17
19
1
2
3
9
10
14
16
18
0
6
8
4
5
7
C L O C K
C K E
H IG H
C S
R A S
C A S
C a
C b
R a
R b
A D D R
A10
A9
R a
R b
W E
D S F
D Q M
D Q C L= 2
Qa3
Qa2
Qa0
Qa2
Qa1
Db3
Db3
Qa1
Qa0
Db0
Db0
Db2
Db1
Qa3
CL = 3
Db1 D b2
Ro w A c t i v e
( A -B an k )
R ea d w it h
Auto Pr ec h ar ge
( A- Ban k )
W r i te wi t h
Auto Pr ec h ar ge
( B- Bank )
Auot Pr ec h ar ge
Star t Poin t
( A- Ban k )
Au ot Pr ec harg e
Star t Poin t
( B- Ba nk )
R o w A c t i v e
(B - B an k )
:D on ' t C ar e
*Note : 1. RDL should be controlled to meet minimum RAS before internal precharge start.
t
t
(In the case of Burst Length = 1 & 2, BRSW mode and Block write)
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2001
Revision : 1.6 43/54
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
