M32L1632512A
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to VSS = 0V)
Parameter
Supply voltage
Symbol
VDD, VDDQ
VIH
Min
3.0
2.0
-0.3
2.4
-
Typ
3.3
3.0
0
Max
Unit
V
Note
3.6
Input high voltage
Input low voltage
Output high voltage
Output low voltage
Input leakage current
VDD+0.3
V
VIL
0.8
-
V
Note 1
IOH = -2mA
IOL = 2mA
Note 2
VOH
-
V
VOL
-
0.4
5
V
IIL
-5
-
µ
Output leakage current
IOL
-5
-
5
Note 3
µ
Output Loading Condition
See Fig 1
Note: 1. VIL(min) = -1.5V AC (pulse width ≤ 5ns)
2. Any input 0V ≤ VIN ≤ VDD + 0.3V, all other pins are not under test = 0V.
4. Dout is disabled, 0V ≤ VOUT ≤ VDD.
CAPACITANCE
(VDD/VDDQ = 3.3V, TA = 25 , f = 1MHZ)
°C
Parameter
Symbol
Min
Max
Unit
Input capacitance (A0 ~ A10)
CIN1
-
4
pF
Input capacitance
CIN2
-
-
4
5
pF
pF
(CLK, CKE, CS , RAS , CAS , WE , DSF& DQM0-3)
Data input/output capacitance (DQ0 ~ DQ31)
COUT
DECOUPLING CAPACITANCE GUIDE LINE
Recommended decoupling capacitance added to power line at board.
Parameter
Symbol
CDC1
Value
Unit
uF
Decoupling Capacitance between VDD & VSS
Decoupling Capacitance between VDDQ & VSSQ
0.1+0.01
0.1+0.01
CDC2
uF
*Note: 1. VDD and VDDQ pins are separated each other.
All VDD pins are connected in chip. All VDDQ pins are connected in chip.
2. VSS and VSSQ pins are separated each other.
All VSS pins are connected in chip. All VSSQ pins are connected in chip.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2001
Revision : 1.6 4/54
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
