M32L1632512A
FUNCTIONAL BLOCK DIAGRAM
MASK
REGISTER
DQMi
BLOCK
WRITE
CONTROL
LOGIC
COLOR
REGISTER
WRITE
CONTROL
LOGIC
MUX
CLK
CKE
DQi
(i=0~31)
COLUMN
MASK
DQMi
CS
RAS
256Kx32
CELL
ARRAY
256Kx32
CELL
ARRAY
CAS
WE
DSF
ROW DECORDER
BANK SELECTION
DQMi
ROW ADDRESS
BUFFER
SERIAL
COUNTER
REFRESH
COUNTER
COLUMN ADDRESS
BUFFER
ADDRESS REGISTER
ADDRESS(A0~A10)
CLOCK
PIN CONFIGURATION (TOP VIEW)
81
A7
50
DQ29
VSSQ
A6
82
83
84
85
86
87
88
49
48
47
46
45
44
43
42
41
40
A5
DQ30
DQ31
VSS
A4
VSS
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N. C
N. C
N. C
N.C
N. C
N. C
N. C
N.C
N.C
1
F
0
o
0
P
in
r d
Q
F
P
e
89
90
91
92
93
94
95
96
97
98
99
100
r w
a
T
y p
2
0
x
1
4
m m
39
38
37
36
35
34
33
32
31
0
. 6
5
m
m
p
i n
P i t c h
N.C
N.C
N.C
VDD
A3
N.C
VDD
DQ0
A2
A1
A0
DQ1
VSSQ
DQ2
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2001
Revision : 1.6 2/54
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
