M32L1632512A
4. CAS Interrupt ( ) : Read Interrupted by Write & DQM
(1) CL=2, BL=4
C L K
i )C M D
R D
R D
R D
W R
D 0
DQ M
D 1
DQ
D 2
D 3
i i )C M D
W R
DQ M
DQ
H i - Z
D 0
D 1
D 2
D 3
i i i )C M D
W R
D Q M
D Q
H i - Z
D 2
D 0
D 3
D 1
W R
i v )C M D
R D
D Q M
DQ
H i - Z
Q 0
D 2
D 0
D 1
D 3
*N o t e 1
(2) CL=3 , BL=4
C L K
i )C M D
R D
W R
D 0
D Q M
D Q
D 3
D 2
D 1
W R
i i )C M D
D Q M
R D
R D
R D
R D
D 0
D 1
D 2
D 3
D Q
i i i )C M D
D Q M
W R
D 0
D 1
D 2
D 3
D 2
D 1
DQ
i v)C M D
D Q M
W R
H i - Z
D 0
D 3
D Q
D 1
W R
v) C M D
D Q M
H i - Z
D 0
D Q
Q 0
D 2
D 3
* N o t e 2
*Note : 1. To prevent bus contention, there should be at least one gap between data in and data out.
2. To prevent bus contention, DQM should be issued which makes at least one gap between data in and data out.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2001
Revision : 1.6 22/54
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
