M32L1632512A
2. DQM Operation
2 ) R e a d M a s k ( B L = 4 )
1 ) W r i t e M a s k ( B L = 4 )
C L K
C M D
W R
R D
D Q M
D Q ( C L 2 )
D Q ( C L3 )
M a s k e d b y D Q M
M a s k e d b y D Q M
D 3
H i - Z
Q 2
Q 1
Q 3
Q 2
D 0
D 0
D 1
D 1
Q 0
H i - Z
D 3
Q 3
D Q M t o D a t a - o u t M a s k = 2
D Q M t o D a t a - i n M a s k = 0 C L K
3 ) D Q M w i t h c l c o k s u s p e n d e d ( F u l l P a g e R e a d )
N o t e 2
C L K
R D
C M D
C K E
D Q M
H i - Z
H i - Z
H i - Z
H i - Z
H i - Z
Q 6
Q 5
Q 8
Q 7
Q 2
Q 1
Q 7
Q 6
Q 4
Q 3
Q 0
D Q ( C L2 )
D Q ( C L 3 )
H i - Z
*Note : 1. There are 4 DQMi (i = 0~3).
Each DQMi masks 8 DQ’s. (1 Byte, 1 Pixel for 8bpp).
2. DQM masks data out Hi-Z after 2 clocks which should masked by CKE “L”.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2001
Revision : 1.6 20/54
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
