M32L1632512A
5. Write Interrupted by Precharge & DQM
C L K
* N o t e 2
C MD
P R E
W R
D 0
* N o t e 1
D Q M
D Q
D 2
D 3
D 1
M a s k e d b y D Q M
*Note : 1. To inhibit invalid write, DQM should be issued.
2. This precharge command and burst write command should be of the same bank, otherwise it is not precharge interrupt
but only another bank precharge of dual banks operation.
6. Precharge
1) Normal Write (BL = 4)
2) Block Write
C L K
C MD
C L K
C MD
P R E
P R E
W R
D 0
B W
DQ
P i x e l
D 2
D 3
D Q
D 1
t B P L
* N o t e 1
t R D L
* N o t e 1
3) Read (BL=4)
C L K
C M D
P R E
R D
1* N o t e 2
Q 3
Q 2
D Q ( C L 2 )
D Q ( C L 3 )
Q 0
Q 1
Q 2
Q 1
2
Q 0
Q 3
7. Auto Precharge
1) Normal Write (BL = 4)
2) Block Write
C L K
C MD
D Q
C L K
C M D
DQ
B W
W R
D 0
D 2
D 3
D 1
P i x e l
t B P L
t R P
t B A L
* N o t e 3
A u t o P r e c h a r g e s t a r t s
* N o t e 3
Au t o P r e c h a r g e s t a r t s
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2001
Revision : 1.6 23/54
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
