ESMT
Switching Characteristics Over the Operating Range[9, 10, 11, 15, 14]
Parameter
Write Cycle[15]
t
WC
t
SCE
t
AW
t
CD
t
HA
t
SA
t
PWE
t
BW
t
SD
t
HD
t
HZWE
t
LZWE
Note:
Write Cycle Time
CE1 LOW and CE2 HIGH to Write End
Address Set-Up to Write End
Chip Deselect Time CE1 = HIGH or CE2 = LOW,
BLE
/
BHE
High Pulse Time
Address Hold from Write End
Address Set-Up to Write Start
WE
Pulse Width
BLE
/
BHE
LOW to Write End
Data Set-Up to Write End
Data Hold from Write End
WE
LOW to High-Z[10, 11, 12]
WE
HIGH to Low-Z[10, 11, 12]
M24D16161DA
(continued)
-70
Min.
70
60
60
15
0
0
50
60
25
0
25
10
Max.
40000
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
15. The internal Write time of the memory is defined by the overlap of
WE
, CE1 = V
IL
or CE2 = V
IH
,
BHE
and/or
BLE
= V
IL
.
All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data
input set-up and hold timing should be referenced to the edge of the signal that terminates the write.
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Jul. 2007
Revision
:
1.0
6/12
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
