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M24D16161DA 参数 Datasheet PDF下载

M24D16161DA图片预览
型号: M24D16161DA
PDF下载: 下载PDF文件 查看货源
内容描述: 16兆位( 1M ×16 )伪静态RAM [16-Mbit (1M x 16) Pseudo Static RAM]
分类和应用:
文件页数/大小: 12 页 / 350 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
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ESMT
AC Test Loads and Waveforms
M24D16161DA
Parameters
R1
R2
R
TH
V
TH
1.8V V
CC
14000
14000
7000
1.90
Unit
V
Switching Characteristics Over the Operating Range[9, 10, 11, 15, 14]
Parameter
Read Cycle
t
RC
[13]
t
CD
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
DBE
t
LZBE
t
HZBE
Read Cycle Time
Chip Deselect Time CE1 =HIGH or CE2=LOW,
BLE
/
BHE
High Pulse Time
Address to Data Valid
Data Hold from Address Change
Description
-70
Min.
70
15
70
5
70
35
5
25
10
25
70
5
25
Max.
40000
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE1 LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z[10, 11, 12]
OE HIGH to High Z[10, 11, 12]
CE1 LOW and CE2 HIGH to Low Z[10, 11, 12]
CE1 HIGH and CE2 LOW to High Z[10, 11, 12]
BLE
/
BHE
LOW to Data Valid
BLE
/
BHE
LOW to Low Z[10, 11, 12]
BLE
/
BHE
HIGH to High Z[10, 11, 12]
Notes:
9. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1 ns/V, timing reference
levels of V
CC(typ.)
/2, input pulse levels of 0V to V
CC
, and output loading of the specified I
OL
/I
OH
as shown in the “AC Test Loads
and Waveforms” section.
10. At any given temperature and voltage conditions t
HZCE
is less than t
LZCE
, t
HZBE
is less than t
LZBE
, t
HZOE
is less than t
LZOE
, and
t
HZWE
is less than t
LZWE
for any given device. All low-Z parameters will be measured with a load capacitance of 30 pF (3V).
11. t
HZOE
, t
HZCE
, t
HZBE
, and t
HZWE
transitions are measured when the outputs enter a high-impedance state.
12. High-Z and Low-Z parameters are characterized and are not 100% tested.
13 .If invalid address signals shorter than min. t
RC
are continuously repeated for 40 µs, the device needs a normal read timing
(t
RC
) or needs to enter standby state at least once in every 40 µs.
14. In order to achieve 70-ns performance, the read access must be Chip Enable ( CE1 or CE2) controlled. That is, the
addresses must be stable prior to Chip Enable going active.
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Jul. 2007
Revision
:
1.0
5/12