ESMT
M24D16161DA
Switching Waveforms (continued)
Write Cycle 4 (BHE/BLE Controlled, OE LOW)[15, 16, 20, 21]
Truth Table[22]
CE2
Inputs/Outputs
High Z
High Z
High Z
Mode
Power
CE1
H
X
OE
X
X
WE
X
X
BHE
X
X
BLE
X
X
X
L
X
Deselect/Power-Down
Deselect/Power-Down
Deselect/Power-Down
Standby (ISB
Standby (ISB
Standby (ISB
)
)
)
X
X
X
H
H
L
H
H
L
L
L
Data Out (I/O0–I/O15)
Read
Read
Read
Active (ICC
)
Data Out (I/O0–I/O7);
(I/O8–I/O15) in High Z
Data Out (I/O8–I/O15);
(I/O0–I/O7) in High Z
L
H
H
L
H
L
Active (ICC
)
L
H
H
L
L
H
Active (ICC
)
L
L
L
H
H
H
H
H
H
H
H
H
L
H
L
L
L
High Z
High Z
High Z
Output Disabled
Output Disabled
Output Disabled
Active (ICC
Active (ICC
Active (ICC
)
)
)
H
Write (Upper Byte and Lower
Byte)
L
L
L
H
H
H
L
L
L
X
X
X
L
H
L
L
L
Data In (I/O0–I/O15)
Active (ICC
Active (ICC
Active (ICC
)
)
)
Data In (I/O0–I/O7);
(I/O8–I/O15) in High Z
Data Out (I/O8–I/O15);
(I/O0–I/O7) in High Z
Write (Lower Byte Only)
Write (Upper Byte Only)
H
Notes:
22.H = Logic HIGH, L = Logic LOW, X = Don’t Care.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2007
Revision : 1.0 10/12