ESMT
AC Operating Test Conditions
Parameter
Input reference voltage for clock (V
REF
)
Input signal maximum peak swing
Input signal minimum slew rate
Input levels (V
IH
/V
IL
)
Input timing measurement reference level
Output timing reference level
Value
0.5*V
DDQ
1.5
1.0
V
REF
+0.31/V
REF
-0.31
V
REF
V
TT
M13S5121632A (2A)
Unit
V
V
V/ns
V
V
V
AC Timing Parameter & Specifications
(V
DD
= 2.3V~2.7V, V
DDQ
= 2.3V~2.7V, T
A
=0 °C ~ 70 °C )
-4
min
CL2
Clock Period
CL2.5
CL3
Access time from CLK/ CLK
CLK high-level width
CLK low-level width
Data strobe edge to clock edge
Clock to first rising edge of DQS delay
Data-in and DM setup time (to DQS)
Data-in and DM hold time (to DQS)
DQ and DM input pulse width (for each
input)
Input setup time
Input hold time
DQS input high pulse width
DQS input low pulse width
DQS falling edge to CLK rising-setup time
DQS falling edge from CLK rising-hold time
Parameter
Symbol
7.5
t
CK
6
4
t
AC
t
CH
t
CL
t
DQSCK
t
DQSS
t
DS
t
DH
t
DIPW
t
IS
t
IH
t
DQSH
t
DQSL
t
DSS
t
DSH
t
DQSQ
t
HZ
t
LZ
-0.7
0.45
0.45
-0.6
0.72
0.5
0.5
1.75
0.6
0.6
0.35
0.35
0.2
0.2
-
-0.7
-0.7
-5
max
13
13
10
+0.7
0.55
0.55
+0.6
1.28
-
-
-
-
-
-
-
-
-
0.40
+0.7
+0.7
min
7.5
6
5
-0.7
0.45
0.45
-0.6
0.72
0.5
0.5
1.75
0.6
0.6
0.35
0.35
0.2
0.2
-
-0.7
-0.7
max
13
13
10
+0.7
0.55
0.55
+0.6
1.28
-
-
-
-
-
-
-
-
-
0.40
+0.7
+0.7
Unit
Note
ns
ns
t
CK
t
CK
ns
t
CK
ns
ns
ns
ns
ns
t
CK
t
CK
t
CK
t
CK
ns
ns
ns
1
1
5
5
Data strobe edge to output data edge
Data-out high-impedance window from
CLK/ CLK
Data-out low-impedance window from
CLK/ CLK
Elite Semiconductor Memory Technology Inc.
Publication Date : May 2012
Revision : 1.1
6/47
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
