ESMT
AC Timing Parameter & Specifications-continued
Parameter
Half Clock Period
DQ-DQS output hold time
Data hold skew factor
ACTIVE to PRECHARGE command
Row Cycle Time
AUTO REFRESH Row Cycle Time
ACTIVE to READ,WRITE delay
PRECHARGE command period
ACTIVE to READ with AUTO
PRECHARGE command
ACTIVE bank A to ACTIVE bank B
command
Write recovery time
Write data in to READ command delay
Average periodic refresh interval
Write preamble
Write postamble
DQS read preamble
DQS read postamble
Clock to DQS write preamble setup time
Load Mode Register / Extended Mode
register cycle time
Exit self refresh to READ command
Exit self refresh to non-READ command
Autoprecharge write recovery+Precharge
time
Symbol
min
t
HP
t
QH
t
QHS
t
RAS
t
RC
t
RFC
t
RCD
t
RP
t
RAP
t
RRD
t
WR
t
WTR
t
REFI
t
WPRE
t
WPST
t
RPRE
t
RPST
t
WPRES
t
MRD
t
XSRD
t
XSNR
t
DAL
t
CL
min or
t
CH
min
t
HP
-t
QHS
-
36
52
60
16
16
15
8
15
2
-
0.25
0.4
0.9
0.4
0
2
200
75
(t
WR
/t
CK
) +
(t
RP
/t
CK
)
-4
max
-
-
0.5
70K
-
-
-
-
-
-
-
-
7.8
-
0.6
1.1
0.6
-
-
-
-
-
M13S5121632A (2A)
-5
min
t
CL
min or
t
CH
min
t
HP
-t
QHS
-
40
55
70
15
15
15
10
15
2
-
0.25
0.4
0.9
0.4
0
2
200
75
(t
WR
/t
CK
) +
(t
RP
/t
CK
)
max
-
-
0.5
70K
-
-
-
-
-
-
-
-
7.8
-
0.6
1.1
0.6
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
CK
us
t
CK
t
CK
t
CK
t
CK
ns
t
CK
t
CK
ns
t
CK
6
4
3
2
Unit
Note
Note:
1. t
HZ
and t
LZ
transitions occur in the same access time windows as valid data transitions. These parameters are not referenced
to a specific voltage level, but specify when the device output is no longer driving (HZ), or begins driving (LZ).
2. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but
system performance (bus turnaround) will degrade accordingly.
3. The specific requirement is that DQS be valid (HIGH, LOW, or at some point on a valid transition) on or before this CLK edge.
A valid transition is defined as monotonic, and meeting the input slew rate specifications of the device. When no writes were
previously in progress on the bus, DQS will be transitioning from High-Z to logic LOW. If a previous write was in progress,
DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on t
DQSS
.
4. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device.
5.
6.
For command/address and CLK & CLK slew rate > 1.0V/ns.
For each of the terms above, if not already an integer, round to the next highest integer.
Elite Semiconductor Memory Technology Inc.
Publication Date : May 2012
Revision : 1.1
7/47
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
