ESMT
M13S32321A (2G)
Write with Auto Precharge
If A8 is high when write command is issued, the write with auto-precharge function is performed. Any new command to the same
bank should not be issued until the internal precharge is completed. The internal precharge begins at the rising edge of the CLK with
the tWR delay after the last data-in.
<Burst Length = 4>
0
1
2
3
4
5
6
7
8
C L K
C L K
B a n k
A
Write A
Auto Precharge
N O P
N O P
N O P
N O P
N O P
N O P
N O P
C O M M A N D
A C T I V E
D Q S
*Bank can be reactivated
at completion of tRP
D
IN 2
DIN 3
D Q ' s
D
IN 1
D
IN 0
t
W R
t
R P
I n t e r n a l p r e c h a r g e s t a r t
At burst read / write with auto precharge, CAS interrupt of the same bank is illegal.
For the same bank
Asserted
For the different bank
Command
4
5
6
7
8
4
5
6
7
8
WRITE
WRITE
WRITE
Illegal
Illegal
Illegal
Legal
Legal
Legal
Legal
Legal
Legal
WRITE
with AP
WRITE
with AP
WRITE with AP*1
Illegal
Illegal
READ
Illegal
Illegal
Legal
Illegal
Legal
Illegal
Legal
Legal
Legal
Legal
READ +
DM*2
READ+
DM
READ
Illegal
Illegal
Illegal
Illegal
READ
with AP+ with AP+
READ
READ
with AP
READ with AP
Illegal
Illegal
Illegal
Legal
Legal
DM
DM
Active
Illegal
Illegal
Illegal
Illegal
Illegal
Illegal
Illegal
Illegal
Legal
Legal
Legal
Legal
Legal
Legal
Legal
Legal
Legal
Legal
Precharge
Illegal
Illegal
Note: 1. AP = Auto Precharge
2. DM: Refer to “Write Interrupted by a Read & DM“
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2012
Revision : 1.0 26/48
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
