ESMT
M13S2561616A (2S)
Operation Temperature Condition -40°C~85°C
Power up & Initialization Sequence (based on DDR400)
VDD
V
DDQ
t
VDT >=0
VTT
(system*)
V
REF
t
C K
t
C L
t
C H
CLK
CLK
t
I S
t
I H
CKE
LVC OMS LO W LE VE L
t
I S
t
I H
ACT
AR
MRS
AR
PRE
NOP
PRE
EMRS
MRS
COMMAND
DM
t
I S
t
I H
A0-A9
A11-An
RA
RA
BA
CODE
CODE
CODE
CODE
CODE
t
I S
t
I S
t
I H
t
I H
t
I S
t
I H
A1 0
CODE
ALL BANKS
ALL BANKS
t
I H
t
I S
BA0 , BA1
BA0=L,
BA1=L
BA0=L,
BA1=L
BA0=H,
BA1=L
H i g h - Z
H i g h -Z
D Q S
D Q
t
M R D
t
M R D
t
R P
t
R F C
t
R F C
t
M R D
T = 2 0 0 u s
2 0 0 cyc l e s o f C L K * *
E x t e n d e d
M o d e
Re g i s t e r
S e t
P o w e r - u p :
V D D a n d
C L K st a b l e
L o a d
M o d e
R e g i s t e r
( wi t h A 8 = L )
L o a d
Mo de
Re g ist e r
Re set DL L
(wi th A8 = H)
:
D o n ’ t c a r e
1 0 1 2 2 B 1 6 R . B
Notes:
* = VTT is not applied directly to the device, however tVTD must be greater than or equal to zero to avoid device latch-up.
** = tMRD is required before any command can be applied, and 200 cycles of CLK are required before an executable
command can be applied. The two Auto Refresh commands may be moved to follow the first MRS but precede the
second PRECHARGE ALL command.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jan. 2015
Revision : 1.0 43/49
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
