ESMT
M12S64322A
Self refresh entry command
CLK
CKE
( CS ,RAS , CAS , CKE = Low , WE = High)
CS
After the command execution, self refresh operation continues while CKE
remains low. When CKE goes to high, the DRAM exits the self refresh mode.
During self refresh mode, refresh interval and refresh operation are performed
internally, so there is no need for external control.
RAS
CAS
Before executing self refresh, all banks must be precharged.
WE
BA0, BA1
(Bank select)
A10
Add
Fig. 7 Self refresh entry
command
Burst stop command
CLK
H
CKE
CS
( CS , WE = Low, RAS , CAS = High)
This command terminates the current burst operation.
Burst stop is valid at every burst length.
RAS
CAS
WE
BA0, BA1
(Bank select)
A10
Add
Fig. 8 Burst stop command
CLK
No operation
CKE
H
CS
RAS
CAS
WE
( CS = Low ,RAS , CAS , WE = High)
This command is not a execution command. No operations begin or terminate by
this command.
BA0, BA1
(Bank select)
A10
Add
Fig. 9 No operation
Elite Semiconductor Memory Technology Inc.
Publication Date: May. 2007
Revision: 1.0 17/46
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
