ESMT
M12S64322A
3. CAS Interrupt (I)
* N o t e 1
1 ) R e a d i n t e r r u p t e d b y R e a d ( B L = 4 )
CL K
C M D
A D D
R D
B
R D
A
DQ ( C L 2 )
DQ ( C L 3 )
QB1 QB2 QB3
QB0 QB1 QB2
QB0
QA0
QA0
QB3
tC C D
* N o t e
2
2 ) W r i t e i n t e r r u p t e d b y W r i t e ( B L = 2 )
3 ) W r i t e i n t e r r u p t e d b y R e a d ( B L = 2 )
CLK
C M D
W R
R D
W R
W R
tC C D * N o t e
B
A
2
tC C D * N o t e
2
A D D
D Q
A
B
DQ ( C L 2 )
DQ ( C L 3 )
DB1
DA0 DB0
tC D L
DQ0
DA0
DA0
DQ1
DQ0
* N o t e
3
DQ1
tC D L
* N o t e
3
*Note : 1. By “interrupt” is meant to stop burst read/write by external before the end of burst.
By ” CAS interrupt ”, to stop burst read/write by CAS access ; read and write.
2. tCCD : CAS to CAS delay. (=1CLK)
3. tCDL : Last data in to new column address delay. (=1CLK)
Elite Semiconductor Memory Technology Inc.
Publication Date: May. 2007
Revision: 1.0 19/46
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
