ESMT
M12S64322A
COMMANDS
CLK
Mode register set command
H
CKE
( CS ,RAS , CAS , WE = Low)
CS
RAS
CAS
The DRAM has a mode register that defines how the device operates. In this
command, A0 through A10 and BA0~BA1 are the data input pins. After power on, the
mode register set command must be executed to initialize the device.
The mode register can be set only when all banks are in idle state.
During 2CLK following this command, the DRAM cannot accept any other
commands.
WE
BA0, BA1
(Bank select)
A10
Add
Fig. 1 Mode register set
command
Activate command
CLK
( CS ,RAS = Low, CAS , WE = High)
H
CKE
The DRAM has four banks, each with 2,048 rows.
This command activates the bank selected by BA1 and BA0 and a row address
selected by A0 through A10.
CS
RAS
CAS
This command corresponds to a conventional DRAM’s RAS falling.
WE
BA0, BA1
(Bank select)
Row
Row
A10
Add
Fig. 2 Row address stroble and
bank active command
CLK
Precharge command
H
CKE
( CS ,RAS , WE = Low, CAS = High )
CS
RAS
CAS
WE
This command begins precharge operation of the bank selected by BA1 and BA0.
When A10 is High, all banks are precharged, regardless of BA1 and BA0. When A10
is Low, only the bank selected by BA1 and BA0 is precharged.
After this command, the DRAM can’t accept the activate command to the
precharging bank during tRP (precharge to activate command period).
This command corresponds to a conventional DRAM’s RAS rising.
BA0, BA1
(Bank select)
A10
(Precharge select)
Add
Fig. 3 Precharge command
Elite Semiconductor Memory Technology Inc.
Publication Date: May. 2007
Revision: 1.0
15/46
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
