M12L16161A
Read & Write Cycle at Same Bank @Burst Length = 4
0
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
C LO C K
HIG H
C KE
*Note 1
tRC
CS
RAS
CAS
tRCD
*Note 2
ADDR
R b
C a 0
R a
C b 0
BA
A1 0 / AP
C L=2
R b
R a
t O H
Q a 1
Q a 2
Q a 3
Q a 2
D b 3
D b 2
D b 1
Q a 0
D b 0
D b 0
tRAC
*Note 4
tS H Z
QC
*Note 3
tS AC
t R D L
t O H
C L=3
D b 2
Q a 0
Q a 1
Q a 3
D b 3
D b 1
tRAC
*Not e4
tS AC
t S H Z
*Note 3
t R D L
WE
DQM
Pr ec h a r g e
(A-B a n k )
Pr e c h a r g e
(A-B a n k )
Ro w Ac tive
(A-Ba n k )
Ro w Ac t ive
(A-Ba n k )
R ea d
(A-B a n k )
Wr it e
(A-B a n k )
: D o n 't c a r e
1.Minimum row cycle times is required to complete internal DRAM operation.
*Note:
2.Row precharge can interrupt burst on any cycle. [CAS Latency-1] number of valid output data is available after Row
precharge. Last valid output will be Hi-Z(tSHZ) after the clock.
3.Access time from Row active command. tcc*(tRCD +CAS latency-1)+tSAC
4.Ouput will be Hi-Z after the end of burst.(1,2,4,8 bit burst)
Burst can’t end in Full Page Mode.
:
Publication Da te J an. 2000
Elite Semiconductor Memory Technology Inc.
P.14
:
Revis ion 1.3u
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
