ESMT
M12L16161A
Operation temperature condition -40℃~85℃
Read & Write Cycle at Different Bank @ Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
18
15
16
17
19
CLOCK
CKE
HIGH
tRRD
C S
R A S
CAS
ADDR
RAc
RAa
CAa
RBb
CBb
CAc
BA
RAa
RBb
RAc
A10/AP
CL=2
*Note1
tCDL
QAa0 QAa1 QAa2 QAa3
DBb0 DBb1 DBb2 DBb3
DBb0 DBb1 DBb2 DBb3
QAc0 QAc1 QAc2
QAc0 QAc1
DQ
QAa1
CL=3
WE
QAa0
QAa2 QAa3
DQM
Write
(B-Bank)
Read
(A-Bank)
Read
(A-Bank)
Precharge
(A-Bank)
Row Active
(A-Bank)
Row Active
(A-Bank)
Row Active
(B-Bank)
: D o n ' t C a r e
*Note: 1.tCDL should be met to complete write.
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2007
Revision : 1.1 18/29