ESMT
M12L128168A
Current
BA
ADDR
ACTION
Note
CS RAS CAS WE
State
H
L
L
L
L
L
L
H
L
L
L
L
L
L
H
L
L
L
L
H
L
L
L
L
X
H
H
H
L
X
H
H
L
X
H
L
X
X
X
NOP ꢁIdle after tRP
Read with
Auto
X
NOP ꢁIdle after tRP
ILLEGAL
X
X
2
2
2
4
Precharge
X
H
L
BA
BA
BA
X
CA
ILLEGAL
H
H
L
RA
ILLEGAL
L
A10/AP
NOP ꢁIdle after tRPL
ILLEGAL
L
X
X
H
L
X
X
H
H
H
L
X
H
H
L
X
X
NOP ꢁRow Active after tRCD
NOP ꢁRow Active after tRCD
ILLEGAL
X
X
Row
X
X
2
2
2
2
Activating
X
H
L
BA
BA
BA
X
CA
ILLEGAL
H
H
L
RA
ILLEGAL
L
A10/AP
ILLEGAL
L
X
X
X
X
X
X
X
H
L
X
X
X
X
X
X
X
X
X
X
X
ILLEGAL
X
H
H
L
X
H
L
X
NOP ꢁIdle after tRFC
NOP ꢁIdle after tRFC
ILLEGAL
X
Refreshing
X
H
L
X
ILLEGAL
L
X
ILLEGAL
X
H
H
H
L
X
H
H
L
X
NOP ꢁIdle after 2clocks
NOP ꢁIdle after 2clocks
ILLEGAL
Mode
X
Register
Accessing
X
X
X
X
ILLEGAL
X
X
ILLEGAL
Abbreviations :
RA = Row Address
NOP = No Operation Command
BA = Bank Address
CA = Column Address
AP = Auto Precharge
*Note : 1. All entries assume the CKE was active (High) during the precharge clock and the current clock cycle.
2. Illegal to bank in specified state ; Function may be legal in the bank indicated by BA, depending on the state of the
bank.
3. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
4. NOP to bank precharge or in idle state. May precharge bank indicated by BA (and A10/AP).
5. Illegal if any bank is not idle.
Elite Semiconductor Memory Technology Inc.
Publication Date: Oct. 2006
Revision: 2.0 25/43
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
