ESMT
M12L128168A
FUNCTION TURTH TABLE (TABLE 1)
Current
WE
BA
ADDR
ACTION
Note
CS RAS CAS
State
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
H
L
L
L
L
L
X
H
H
H
L
X
H
H
L
X
H
L
X
X
X
X
X
NOP
NOP
X
ILLEGAL
2
2
IDLE
X
H
L
BA
BA
BA
X
CA, A10/AP ILLEGAL
H
H
L
RA
Row (&Bank) Active ; Latch RA
L
A10/AP
NOP
4
5
5
L
H
L
X
Auto Refresh or Self Refresh
L
L
OP code
X
OP code
Mode Register Access
X
H
H
H
H
L
X
H
H
L
X
H
L
X
X
X
NOP
X
NOP
X
ILLEGAL
2
2
Row
H
L
BA
BA
BA
BA
X
CA, A10/AP Begin Read ; latch CA ; determine AP
CA, A10/AP Begin Write ; latch CA ; determine AP
Active
L
H
H
L
H
L
RA
ILLEGAL
L
A10/AP
Precharge
L
X
X
H
L
X
X
X
X
ILLEGAL
X
H
H
H
H
L
X
H
H
L
X
NOP (Continue Burst to End ꢁRow Active)
NOP (Continue Burst to End ꢁRow Active)
Term burst ꢁRow active
X
X
Read
Write
H
L
BA
BA
BA
BA
X
CA, A10/AP Term burst, New Read, Determine AP
CA, A10/AP Term burst, New Write, Determine AP
L
3
2
H
H
L
H
L
RA
ILLEGAL
L
A10/AP
Term burst, Precharge timing for Reads
ILLEGAL
L
X
X
H
L
X
X
X
X
X
H
H
H
H
L
X
H
H
L
X
NOP (Continue Burst to End ꢁRow Active)
NOP (Continue Burst to End ꢁRow Active)
Term burst ꢁRow active
X
X
H
L
BA
BA
BA
BA
X
CA, A10/AP Term burst, New Read, Determine AP
CA, A10/AP Term burst, New Write, Determine AP
3
3
2
3
L
H
H
L
H
L
RA
ILLEGAL
L
A10/AP
Term burst, Precharge timing for Writes
ILLEGAL
L
X
X
H
L
X
X
X
X
X
H
H
H
L
X
H
H
L
X
NOP (Continue Burst to End ꢁRow Active)
NOP (Continue Burst to End ꢁRow Active)
ILLEGAL
Read with
Auto
X
X
Precharge
X
X
X
X
H
L
BA
BA
X
CA, A10/AP ILLEGAL
H
L
RA, RA10
ILLEGAL
2
2
L
X
X
X
X
ILLEGAL
X
H
H
H
L
X
H
H
L
X
NOP (Continue Burst to End ꢁRow Active)
NOP (Continue Burst to End ꢁRow Active)
ILLEGAL
Write with
Auto
X
X
Precharge
X
X
X
BA
BA
X
CA, A10/AP ILLEGAL
H
L
RA, RA10
X
ILLEGAL
ILLEGAL
L
Elite Semiconductor Memory Technology Inc.
Publication Date: Oct. 2006
Revision: 2.0
24/43
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
