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F49L160UA_1 参数 Datasheet PDF下载

F49L160UA_1图片预览
型号: F49L160UA_1
PDF下载: 下载PDF文件 查看货源
内容描述: 16兆位( 2M ×8 / 1M ×16 ) 3V只有CMOS闪存 [16 Mbit (2M x 8/1M x 16) 3V Only CMOS Flash Memory]
分类和应用: 闪存
文件页数/大小: 51 页 / 459 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
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ESMT  
F49L160UA/F49L160BA  
Operation Temperature condition -40°C~85°C  
7.4 More Device Operations  
Hardware Data Protection  
Write cycles are inhibited by holding any one of  
=
OE  
V ,  
IL  
= V or  
= V . To initiate a write cycle,  
WE  
CE  
and  
IH  
IH  
The command sequence requirement of unlock cycles for  
programming or erasing provides data protection against  
inadvertent writes. In addition, the following hardware  
data protection measures prevent accidental erasure or  
programming, which might otherwise be caused by  
must be a logical zero while  
is a  
OE  
WE  
CE  
logical one.  
Power Supply Decoupling  
spurious system level signals during V  
power-up and  
CC  
power-down transitions, or from system noise.  
In order to reduce power switching effect, each device  
should have a 0.1uF ceramic capacitor connected  
between its V  
and GND.  
CC  
Low VCC Write Inhibit  
When V  
is less than VLKO, the device does not accept  
CC  
Power-Up Sequence  
any write cycles. This protects data during V  
power-up  
CC  
and power-down. The command register and all internal  
program/erase circuits are disabled, and the device  
The device powers up in the Read Mode. In addition, the  
memory contents may only be altered after successful  
completion of the predefined command sequences.  
resets. Subsequent writes are ignored until V  
is  
CC  
greater than V  
. The system must provide the proper  
LKO  
signals to the control pins to prevent unintentional writes  
Power-Up Write Inhibit  
when V is greater than V  
.
LKO  
CC  
If  
=
= V and  
= V during power up, the  
OE  
IH  
WE  
device does not accept commands on the rising edge of  
. The internal state machine is automatically reset to  
CE  
IL  
Write Pulse "Glitch" Protection  
WE  
reading array data on power-up.  
Noise pulses of less than 5 ns (typical) on  
do not initiate a write cycle.  
or  
WE  
CE  
Logical Inhibit  
Elite Semiconductor Memory Technology Inc.  
Publication Date : Jan. 2008  
Revision: 1.4 18/51  
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