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F49L160UA_1 参数 Datasheet PDF下载

F49L160UA_1图片预览
型号: F49L160UA_1
PDF下载: 下载PDF文件 查看货源
内容描述: 16兆位( 2M ×8 / 1M ×16 ) 3V只有CMOS闪存 [16 Mbit (2M x 8/1M x 16) 3V Only CMOS Flash Memory]
分类和应用: 闪存
文件页数/大小: 51 页 / 459 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
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ESMT  
F49L160UA/F49L160BA  
Operation Temperature condition -40°C~85°C  
Output Enable (  
) is asserted low. Refer to Figure  
OE  
RY/BY :  
Ready/Busy  
21, Data Polling Timings (During Embedded  
Algorithms), Figure 19 shows the Data Polling  
algorithm.  
The RY/  
is a dedicated, open-drain output pin that  
BY  
indicates whether an Embedded Algorithm is in  
progress or complete. The RY/ status is valid after  
DQ6:Toggle BIT I  
BY  
pulse in the command  
Toggle Bit I on DQ6 indicates whether an Embedded  
Program or Erase algorithm is in progress or complete,  
or whether the device has entered the Erase Suspend  
mode. Toggle Bit I may be read at any address, and is  
the rising edge of the final  
sequence. Since RY/  
several RY/  
WE  
is an open-drain output,  
BY  
pins can be tied together in parallel  
BY  
with a pull-up resistor to V  
.
CC  
valid after the rising edge of the final  
pulse in the  
WE  
command sequence (prior to the program or erase  
operation), and during the sector erase time-out.  
If the output is low (Busy), the device is actively erasing  
or programming. (This includes programming in the  
Erase Suspend mode.) If the output is high (Ready),  
the device is ready to read array data (including during  
the Erase Suspend mode), or is in the standby mode.  
During an Embedded Program or Erase algorithm  
operation, successive read cycles to any address  
cause DQ6 to toggle. The system may use either  
OE  
to control the read cycles. When the operation  
Table 7 shows the outputs for RY/  
.
BY  
or  
CE  
is complete, DQ6 stops toggling.  
DQ7: Data Polling  
When an erase command sequence is written, if all  
sectors selected for erasing are protected, DQ6  
toggles for approximately 100 µs, then returns to  
reading array data. If not all selected sectors are  
protected, the Embedded Erase algorithm erases the  
unprotected sectors, and ignores the selected sectors  
that are protected.  
The DQ7 indicates to the host system whether an  
Embedded Algorithm is in progress or completed, or  
whether the device is in Erase Suspend mode. The  
Data Polling is valid after the rising edge of the final  
pulse in the program or erase command  
WE  
sequence.  
The system can use DQ6 and DQ2 together to  
determine whether a sector is actively erasing or is  
erase-suspended. When the device is actively erasing  
(i.e. the Embedded Erase algorithm is in progress),  
DQ6 toggles. When the device enters the Erase  
Suspend mode, DQ6 stops toggling. However, the  
system must also use DQ2 to determine which sectors  
are erasing or erase-suspended. Alternatively, the  
system can use DQ7.  
During the Embedded Program algorithm, the device  
outputs on DQ7 the complement of the datum  
programmed to DQ7. This DQ7 status also applies to  
programming during Erase Suspend. When the  
Embedded Program algorithm is complete, the device  
outputs the true data on DQ7. The system must provide  
the program address to read valid status information on  
DQ7. If a program address falls within a protected  
sector, Data Polling on DQ7 is active for approximately  
1 µs, then the device returns to reading array data.  
If a program address falls within a protected sector,  
DQ6 toggles for approximately 2 µs after the program  
command sequence is written, then returns to reading  
array data.  
During the Embedded Erase algorithm, Data Polling  
produces a “0” on DQ7. When the Embedded Erase  
algorithm is complete, or if the device enters the Erase  
Suspend mode, Data Polling produces a “1” on DQ7.  
The system must provide an address within any of the  
sectors selected for erasure to read valid status  
information on DQ7.  
DQ6 also toggles during the erase-suspend-program  
mode, and stops toggling once the Embedded  
Program algorithm is complete. Table 7 shows the  
outputs for Toggle Bit I on DQ6. Figure 20 shows the  
toggle bit algorithm. Figure 22 shows the toggle bit  
timing diagrams. Figure 25 shows the differences  
between DQ2 and DQ6 in graphical form. Refer to the  
subsection on DQ2: Toggle Bit II.  
After an erase command sequence is written, if all  
sectors selected for erasing are protected, Data Polling  
on DQ7 is active for approximately 100 µs, then the  
device returns to reading array data. If not all selected  
sectors are protected, the Embedded Erase algorithm  
erases the unprotected sectors, and ignores the  
selected sectors that are protected.  
DQ2: Toggle Bit II  
The “Toggle Bit II” on DQ2, when used with DQ6,  
indicates whether a particular sector is actively erasing  
(that is, the Embedded Erase algorithm is in progress),  
or whether that sector is erase-suspended. Toggle Bit II  
When the system detects DQ7 has changed from the  
complement to true data, it can read valid data at DQ7~  
DQ0 on the following read cycles. This is because DQ7  
may change asynchronously with DQ0–DQ6 while  
is valid after the rising edge of the final WE or CE ,  
whichever happens first, in the command sequence.  
Elite Semiconductor Memory Technology Inc.  
Publication Date : Jan. 2008  
Revision: 1.4  
16/51  
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