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F49L160UA_1 参数 Datasheet PDF下载

F49L160UA_1图片预览
型号: F49L160UA_1
PDF下载: 下载PDF文件 查看货源
内容描述: 16兆位( 2M ×8 / 1M ×16 ) 3V只有CMOS闪存 [16 Mbit (2M x 8/1M x 16) 3V Only CMOS Flash Memory]
分类和应用: 闪存
文件页数/大小: 51 页 / 459 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
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ESMT  
F49L160UA/F49L160BA  
Operation Temperature condition -40°C~85°C  
Reset Command  
Program Command  
Writing the reset command to the device resets the  
device to reading array data. Address bits are all don’t  
cares for this command.  
The program command sequence programs one byte  
into the device. Programming is a four-bus-cycle  
operation. The program command sequence is initiated  
by writing two unlock write cycles, followed by the  
program set-up command. The program address and  
data are written next, which in turn initiate the  
Embedded Program algorithm. The system is not  
required to provide further controls or timings. The  
device automatically provides internally generated  
program pulses and verifies the programmed cell  
margin.  
The reset command may be written between the  
sequence cycles in an erase command sequence  
before erasing begins. This resets the device to reading  
array data. Once erasure begins, however, the device  
ignores reset commands until the operation is  
complete.  
The reset command may be written between the  
sequence cycles in a program command sequence  
before programming begins. This resets the device to  
reading array data (also applies to programming in  
Erase Suspend mode). Once programming begins,  
however, the device ignores reset commands until the  
operation is complete.  
When the Embedded Program algorithm is complete,  
the device then returns to reading array data and  
addresses are no longer latched. The system can  
determine the status of the program operation by using  
DQ7, DQ6, or RY/  
. See “Write Operation Status”  
BY  
section for more information on these status bits.  
The reset command may be written between the  
sequence cycles in an auto-select command sequence.  
Once in the auto-select mode, the reset command must  
be written to return to reading array data (also applies  
to auto-select during Erase Suspend).  
Any commands written to the device during the  
Embedded Program Algorithm are ignored. Note that a  
hardware  
reset  
immediately  
terminates  
the  
programming operation. The Program command  
sequence should be reinitiated once the device has  
reset to reading array data, to ensure data integrity.  
If DQ5 goes high(see “DQ5: Exceeded Timing Limits”  
section) during a program or erase operation, writing  
the reset command returns the device to reading array  
data (also applies during Erase Suspend).  
Programming is allowed in any sequence and across  
sector boundaries. A bit cannot be programmed from a  
“0” back to a “1”. Attempting to do so may halt the  
operation and set DQ5 to “1”, or cause the Data Polling  
algorithm to indicate the operation was successful.  
However, a succeeding read will show that the data is  
still “0”. Only erase operations can convert a “0” to a  
“1”.  
Read Command  
The device is automatically set to reading array data  
after device power-up. No commands are required to  
retrieve data. The device is also ready to read array  
data after completing an Embedded Program or  
Embedded Erase algorithm.  
Chip Erase Command  
Chip erase is a six-bus cycle operation. The chip erase  
command sequence is initiated by writing two unlock  
cycles, followed by a set-up command. Two additional  
unlock write cycles are then followed by the chip erase  
command, which in turn invokes the Embedded Erase  
algorithm.  
When the device accepts an Erase Suspend command,  
the device enters the Erase Suspend mode. The  
system can read array data using the standard read  
timings, except that if it reads an address within  
erase-suspended sectors, the device outputs status  
data. After completing a programming operation in the  
Erase Suspend mode, the system may once again read  
array data with the same exception. See “Erase  
Suspend/Erase Resume Commands” for more  
information on this mode.  
The device does not require the system to preprogram  
prior to erase. The Embedded Erase algorithm  
automatically preprograms and verifies the entire  
memory for an all zero data pattern prior to electrical  
erase.  
The system must issue the reset command to  
re-enable the device for reading array data if DQ5 goes  
high, or while in the auto-select mode. See the “Reset  
Command” section. See also the “Read Mode” in the  
“Device Operations” section for more information. Refer  
to Figure 5 for the timing diagram.  
Any commands written to the chip during the  
Embedded Erase algorithm are ignored. Note that a  
hardware reset during the chip erase operation  
immediately terminates the operation. The Chip Erase  
command sequence should be reinitiated once the  
device has returned to reading array data, to ensure  
the data integrity.  
Elite Semiconductor Memory Technology Inc.  
Publication Date : Jan. 2008  
Revision: 1.4  
13/51  
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