EFST
preliminary
F49L004UA / F49L004BA
Table 12.
Controlled Program/Erase Operations(TA = 0C to 70C, VCC = 2.7V~3.6V)
CE
-70
-90
Symbol
Description
Min.
Max.
Min.
Max.
Unit
Write Cycle Time (Note 1)
Address Setup Time
Address Hold Time
Data Setup Time
70
90
ns
tWC
tAS
0
45
35
0
0
45
35
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
sec
tAH
tDS
Data Hold Time
tDH
Output Enable Setup Time
0
0
tOES
tGHEL
tWS
Read Recovery Time Before Write
0
0
0
0
Setup Time
Hold Time
WE
WE
CE
0
0
tWH
Pulse Width
35
30
35
30
tCP
Pulse Width High
CE
tCPH
tWHWH1
tWHWH2
Programming Operation(note2)
Sector Erase Operation (note2)
9(typ.)
9(typ.)
0.7(typ.)
0.7(typ.)
Notes :
1. Not 100% tested.
2. See the "Erase and Programming Performance" section for more information.
Elite Flash Storage Technology Inc.
Publication Date : Aug. 2003
Revision: 0.2 22/46
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
