EFST
preliminary
F49L004UA / F49L004BA
10.2 Program/Erase Operation
Table 11.
Controlled Program/Erase Operations(TA = 0C to 70C, VCC = 2.7V~3.6V)
WE
-70
-90
Symbol
Description
Unit
Min.
70
Max.
Min.
90
Max.
Write Cycle Time (Note 1)
Address Setup Time
Address Hold Time
Data Setup Time
ns
ns
ns
ns
ns
ns
tWC
tAS
0
45
35
0
0
45
35
0
tAH
tDS
Data Hold Time
tDH
tOES
Output Enable Setup Time
Read Recovery Time Before
0
0
0
0
ns
tGHWL
Write (
High to
low)
WE
OE
Setup Time
Hold Time
0
0
0
0
ns
ns
ns
ns
CE
CE
tCS
tCH
tWP
tWPH
Write Pulse Width
Write Pulse Width High
35
30
35
30
Programming Operation (Note 2)
(Byte program time)
9(typ.)
9(typ.)
us
tWHWH1
Sector Erase Operation (Note 2)
VCC Setup Time (Note 1)
0.7(typ.)
0.7(typ.)
sec
us
tWHWH2
tVCS
50
0
50
0
ns
Recovery Time from RY/
tRB
BY
90
90
ns
Program/Erase Valid to RY/
Delay
BY
tbusy
Notes :
1. Not 100% tested.
2. See the "Erase and Programming Performance" section for more information.
Elite Flash Storage Technology Inc.
Publication Date : Aug. 2003
Revision: 0.2 21/46
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
