EFST
preliminary
F49L004UA / F49L004BA
Figure 9. CE Controlled Program Timing Waveform
5 5 5 f o r p r o g r a mP A f o r p r o g r a m
2 A A f o r e r a s e S A f o r s e c t o r e r a s e
5 5 5 f o r c h i p
e r a sDe ata P ol li n g
P D
Addr es s
tW C
tW H
t A S
tA H
W E
OE
tG H E L
tC P
tW H W H 1 o r
2
C E
tC P H
tD H
t W S
tB U S Y
tD S
Dat a
D O U T
DQ7
P D f o r p r o g r a m
A0 f o r p r o g r a m
5 5 f o r e r a s e
3 0 f o r s e c t o r e r a s e
1 0 f o r c h i p e r a s e
tR H
RE S E T
RY/B Y
Notes :
1. PA = Program Address, PD = Program Data, DOUT = Data Out , DQ7 = complement of data written to device
2. Figure indicates the last two bus cycles of the command sequence..
Elite Flash Storage Technology Inc.
Publication Date : Aug. 2003
Revision: 0.2 26/46
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
