ESMT
(Preliminary)
F25S04PA
STATUS REGISTER
The software status register provides status on whether the flash
memory array is available for any Read or Write operation,
whether the device is Write enabled, and the state of the memory
Write protection. During an internal Erase or Program operation,
the status register may be read only to determine the completion
of an operation in progress. Table 2 describes the function of
each bit in the software status register.
Table 2: Software Status Register
Default at
Power-up
Bit
0
Name
BUSY
WEL
Function
Read/Write
1 = Internal Write operation is in progress
0 = No internal Write operation is in progress
1 = Device is memory Write enabled
0 = Device is not memory Write enabled
0
0
R
R
1
2
3
4
5
6
BP0
BP1
BP2
TB
Indicate current level of block write protection (See Table 3)
Indicate current level of block write protection (See Table 3)
Indicate current level of block write protection (See Table 3)
Top / Bottom write protect
0
0
0
0
0
R/W
R/W
R/W
R/W
N/A
RESERVED Reserved for future use
1 = BP2,BP1,BP0 and TB are read-only bits
0 = BP2,BP1,BP0 and TB are read/writable
7
BPL
0
R/W
Note:
1. Only BP0, BP1, BP2, TB and BPL are writable.
2. BP0, BP1, BP2, TB and BPL are non-volatile; others volatile.
3. All area are protected at power-on (BP2=BP1=BP0=1)
WRITE ENABLE LATCH (WEL)
BUSY
The Write-Enable-Latch bit indicates the status of the internal
memory Write Enable Latch. If this bit is set to “1”, it indicates the
device is Write enabled. If the bit is set to “0” (reset), it indicates
the device is not Write enabled and does not accept any memory
Write (Program/ Erase) commands. This bit is automatically reset
under the following conditions:
The Busy bit determines whether there is an internal Erase or
Program operation in progress. A “1” for the Busy bit indicates
the device is busy with an operation in progress. A “0” indicates
the device is ready for the next valid operation.
• Power-up
Top/Bottom Block Protect (TB)
• Write Disable (WRDI) instruction completion
• Page Program instruction completion
• Sector Erase instruction completion
• Block Erase instruction completion
• Chip Erase instruction completion
• Write Status Register instructions
The Top/Bottom bit (TB) controls if the Block-Protection (BP2,
BP1, BP0) bits protect from the Top (TB=0) or the Bottom (TB=1)
of the array as show in Table 3, The TB bit can be set with Write
Status Register (WRSR) instruction. The TB bit can not be written
to if the Block- Protection-Look (BPL) bit is 1 or WP is low.
Elite Semiconductor Memory Technology Inc.
Publication Date: May 2009
Revision: 0.2
6/34
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
