ESMT
F25L16PA (2S)
4K Byte Sector Erase
The Sector Erase instruction clears all bits in the selected sector
to FFH. A Sector Erase instruction applied to a protected memory
area will be ignored. Prior to any Write operation, the Write
[AMS -A12] (AMS = Most Significant address) are used to determine
the sector address (SAX), remaining address bits can be VIL or
VIH. CE must be driven high before the instruction is executed.
The user may poll the BUSY bit in the Software Status Register
or wait TSE for the completion of the internal self-timed Sector
Erase cycle. See Figure 11 for the Sector Erase sequence.
Enable (WREN) instruction must be executed. CE must remain
active low for the duration of the any command sequence. The
Sector Erase instruction is initiated by executing an 8-bit
command, 20H, followed by address bits [A23 -A0]. Address bits
CE
0
1 2
3
4
5
6
7 8
15 16
23 24
31
MODE3
MODE0
SCK
ADD.
ADD.
ADD.
20
SI
MSB
MSB
HIGH IMPENANCE
SO
Figure 11: 4K-byte Sector Erase Sequence
Chip Erase
The Chip Erase instruction clears all bits in the device to FFH. A
Chip Erase instruction will be ignored if any of the memory area is
protected. Prior to any Write operation, the Write Enable (WREN)
Erase instruction is initiated by executing an 8-bit command, 60H
or C7H. CE must be driven high before the instruction is
executed. The user may poll the BUSY bit in the Software Status
Register or wait TCE for the completion of the internal self-timed
Chip Erase cycle. See Figure 12 for the Chip Erase sequence.
instruction must be executed. CE must remain active low for
the duration of the Chip Erase instruction sequence. The Chip
CE
0 1 2 3 4 5 6 7
MODE3
SCK
SI
MODE0
60 or C7
MSB
HIGH IMPENANCE
SO
Figure 12: Chip Erase Sequence
Elite Semiconductor Memory Technology Inc.
Publication Date: Nov. 2012
Revision: 1.4 20/42
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
