ESMT
F25L08QA (2S)
TABLE 12: LATCH UP CHARACTERISTIC
Symbol
Parameter
Latch Up
Minimum
Unit
Test Method
JEDEC Standard 78
1
ILTH
100 + IDD
mA
Note 1: This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 13: CAPACITANCE (TA = 25°C, f=1 MHz, other pins open)
Parameter
Description
Test Condition
VOUT = 0V
Maximum
8 pF
1
COUT
Output Pin Capacitance
Input Capacitance
1
CIN
VIN = 0V
6 pF
Note 1: This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 14: AC OPERATING CHARACTERISTICS
Normal 33MHz Fast 50 MHz
Fast 86 MHz
Fast 100 MHz
Symbol
Parameter
Unit
Min
Max
Min
Max
Min
Max
Min
Max
FCLK
Serial Clock Frequency
33
50
86
100
MHz
ns
TSCKH
TSCKL
Serial Clock High Time
13
13
0.1
0.1
5
9
9
6
6
4
4
Serial Clock Low Time
ns
2
TCLCH
Clock Rise Time (Slew Rate)
Clock Fall Time (Slew Rate)
0.1
0.1
5
0.1
0.1
5
0.1
0.1
5
V/ns
V/ns
ns
2
TCHCL
1
TCES
CE Active Setup Time
CE Active Hold Time
CE Not Active Setup Time
CE Not Active Hold Time
CE Deselect Time
1
TCEH
5
5
5
5
ns
1
TCHS
5
5
5
5
ns
1
TCHH
5
5
5
5
ns
TCPH
TCHZ
TCLZ
TDS
10
10
10
10
ns
7
7
7
7
ns
CE High to High-Z Output
SCK Low to Low-Z Output
Data In Setup Time
0
2
1
5
5
5
5
0
2
1
5
5
5
5
0
2
1
5
5
5
5
0
2
1
5
5
5
5
ns
ns
TDH
Data In Hold Time
ns
THLS
THHS
THLH
THHH
ns
HOLD Low Setup Time
HOLD High Setup Time
HOLD Low Hold Time
ns
ns
ns
HOLD High Hold Time
HOLD Low to High-Z Output
HOLD High to Low-Z Output
3
THZ
8
8
8
8
8
8
8
8
ns
3
TLZ
ns
Elite Semiconductor Memory Technology Inc.
Publication Date: Nov. 2013
Revision: 1.2 33/43