EN29LV160A
Figure 8. AC Waveforms for /DATA Polling During Embedded Algorithm
Operations
tRC
VA
Addresses
CE#
VA
tACC
VA
tCH
tCE
tOE
OE#
tOEH
tDF
WE#
tOH
Comple-
ment
True
Complement
Status Data
Valid Data
Valid Data
DQ[7]
Status
Data
True
DQ[6:0]
tBUSY
RY/BY#
Notes:
1. VA=Valid Address for reading Data# Polling status data
2. This diagram shows the first status cycle after the command sequence, the last status read cycle and the array data read cycle.
Figure 9. AC Waveforms for Toggle Bit During Embedded Algorithm
Operations
tRC
Addresses
CE#
VA
VA
VA
VA
tACC
tCE
tCH
tOE
OE#
tOEH
tDF
WE#
tOH
Valid Status
(second read)
Valid Data
Valid Status
(first read)
Valid Status
DQ6, DQ2
RY/BY#
tBUSY
(stops toggling)
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc., www.essi.com.tw
36
Rev. I, Issue Date: 2008/07/17
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
