EN29LV160A
Figure 10. Alternate CE# Controlled Write Operation Timings
PA for Program
SA for Sector Erase
0x555 for Chip Erase
0x555 for Program
0x2AA for Erase
Addresses
VA
tWC
tAS
tAH
WE#
OE#
CE#
Data
tWH
tGHEL
tCP
tCPH
tCWHWH1 / tCWHWH2 / tCWHWH3
tWS
tBUSY
tDS
tDH
Status
DOUT
PD for Program
0x30 for Sector Erase
0x10 for Chip Erase
0xA0 for Program
0x55 for Erase
RY/BY#
tRH
Reset#
Notes:
PA = address of the memory location to be programmed.
PD = data to be programmed at byte address.
VA = Valid Address for reading program or erase status
Dout = array data read at VA
Shown above are the last two cycles of the program or erase command sequence and the last status read
cycle
Reset# shown to illustrate tRH measurement references. It cannot occur as shown during a valid command
sequence.
Figure 11. DQ2 vs. DQ6
Enter
Embedded
Erase
Enter Erase
Suspend
Program
Erase
Suspend
Erase
Resume
WE#
Erase
Enter
Suspend
Read
Enter
Suspend
Program
Erase
Suspend
Read
Erase
Complete
Erase
DQ6
DQ2
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc., www.essi.com.tw
37
Rev. I, Issue Date: 2008/07/17
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
