S1D15E06 Series
(7) Page Address Set
This command specifies the page address corresponding to row address when MPU access to the display data RAM
shown in Fig. 6.5 and 6.6. For details, see the description of “6.2.2 Page address circuit” in the Function Description.
E
RD
R/W
WR
A0
0
D7
1
D6
0
D5
1
D4
1
D3
0
D2
0
D1
0
D0
Page address
1
1
0
0
1
Command
1
*
*
P5
P4
P3
P2
P1
P0 Page address setting
*: denote invalid bits.
P5
0
P4
0
P3
0
P2
0
P1
0
P0
0
Page address
0
1
0
0
0
0
0
1
↓
↓
0
1
1
0
1
0
1
0
1
0
1
0
31
32
(8) Column Address Set
This command sets the display data RAM column address given in Fig. 6.5 and 6.6. For details, see the description of
“6.2.3 Column address circuit” in the Function Description.
E
RD
R/W
WR
A0
0
D7
0
D6
0
D5
0
D4
1
D3
0
D2
0
D1
1
D0
1
1
1
0
0
1
P7
P6
P5
P4
P3
P2
P1
P0
Column
address
P7
0
P6
0
P5
0
P4
0
P3
0
P2
0
P1
0
P0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
2
↓
↓
1
1
0
0
0
0
0
1
0
1
0
1
1
1
0
1
158
159
(9) Display Data Write
This command allows the 8-bit data to be written to the address specified by the display data RAM. After writing,
column address or page address is automatically incremented +1 by the Display Data Input Direction Select command.
This enables the MPU to write the display data continuously.
E
RD
R/W
WR
A0
0
D7
D6
D5
D4
D3
D2
D1
D0
1
1
0
0
0
0
0
1
1
1
0
1
1
Write Data
30
EPSON
Rev. 2.1
EPSON [ EPSON COMPANY ]
