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S1D15E06D03E000 参数 Datasheet PDF下载

S1D15E06D03E000图片预览
型号: S1D15E06D03E000
PDF下载: 下载PDF文件 查看货源
内容描述: 直接RAM的数据显示由显示数据RAM [Direct RAM data display by display data RAM]
分类和应用:
文件页数/大小: 74 页 / 668 K
品牌: EPSON [ EPSON COMPANY ]
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S1D15E06 Series  
6. FUNCTIONAL DESCRIPTION  
6.1 MPU Interface  
6.1.1 Selection of Interface Type  
S1D15E06 series allows data to be sent via the 8-bit bi-directional data buses (D7 to D0) or serial data input (SI). By  
setting the polarity of the P/S pin to HIGH or LOW, you can select either 8-bit parallel data input or serial data input,  
as shown in Table 6.1.  
Table 6.1  
P/S  
CS1  
CS2  
CS2  
CS2  
A0  
A0  
A0  
RD  
RD  
WR  
WR  
C86  
C86  
D7  
D7  
SI  
D6  
D6  
D5 to D0  
D5 to D0  
(HZ)  
HIGH : Parallel input CS1  
LOW : Serial input CS1  
SCL  
: Fixed to HIGH or LOW HZ: High impedance state  
6.1.2 parallel interface  
When the parallel interface is selected (P/S = HIGH), direction connection to the MPU bus of either 80 series MPU or  
68 series MPU is performed by setting the 86 pin to either HIGH or LOW, as shown in Table 6.2.  
Table 6.2  
P/S  
CS1  
CS1  
CS1  
CS2  
CS2  
CS2  
A0  
A0  
A0  
RD  
E
WR  
R/W  
WR  
D7 to D0  
D7 to D0  
D7 to D0  
HIGH : 68 series MPU bus  
LOW : 80 series MPU bus  
RD  
The data bus signals are identified by a combination of A0, RD (E), and WR (R/W) signals as shown in Table 6.3.  
Table 6.3  
Common 68 series  
80 series  
WR  
Function  
A0  
1
R/W  
RD  
0
1
0
1
1
0
0
Display data read, status read  
Display data write, command parameter write  
Command write  
1
1
0
1
6.1.3 Serial interface  
When the serial interface is selected (P/S =LOW), the chip is active (CS1 = LOW, CS2 = HIGH), and reception of serial  
data input (SI) and serial clock input (SCL) is enabled. Serial interface comprises a 8-bit shift register and 3-bit counter.  
The serial data are latched by the rising edge of serial clock signals in the order of D7, D6, .... and D0 starting from the  
serial data input pin. On the rising edge of 8th serial clock signal, they are converted into 8-bit parallel data to be  
processed.  
Whether serial data input is a display data or command is identified by A0 input. A0 = HIGH indicates display data,  
while A0 = LOW shows command data. The A0 input is read and identified at every 8 × n-th rising edge of the serial  
clock after the chip has turned active.  
Fig. 6.1 shows the serial interface signal chart.  
Rev. 2.1  
EPSON  
11  
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