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S1D15E06D03E000 参数 Datasheet PDF下载

S1D15E06D03E000图片预览
型号: S1D15E06D03E000
PDF下载: 下载PDF文件 查看货源
内容描述: 直接RAM的数据显示由显示数据RAM [Direct RAM data display by display data RAM]
分类和应用:
文件页数/大小: 74 页 / 668 K
品牌: EPSON [ EPSON COMPANY ]
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S1D15E06 Series  
5.3 System Bus Connection Pin  
Number of  
pins  
Pin name  
I/O  
Description  
D7 to D0  
I/O  
Connects to the 8-bit or 16-bit MPU data bus via the 8-bit  
bi-directional data bus.  
8
(SI)  
(SCL)  
When the serial interface is selected (P/S = LOW), D7 serves as the  
serial data input (SI) and D6 serves as the serial clock input (SCL),  
In this case, D0 through D5 go to a high impedance state. When the  
Chip select is inactive, D0 through D7 go to a high impedance state.  
A0  
I
Normally, the least significant bit MPU address bus is connected  
to distinguish between data and command.  
1
A0 = HIGH : indicates that D0 to D7 are display data or command parameters.  
A0 = LOW : indicates that D0 to D7 are control commands.  
RES  
I
I
I
When the RES is LOW, initialization is achieved.  
Resetting operation is done on the level of the RES signal.  
1
2
1
CS1  
CS2  
A chip select signal. When CS1 = LOW and CS2 = HIGH, signals  
are active, and data/command input/output are enabled.  
RD  
(E)  
When the 80 series MPU is connected.  
A pin for connection of the RD signal of the 80 series MPU.  
When this signal is LOW, the data bus of the S1D15E06 series  
is in the output state.  
When the 68 series MPU is connected.  
Serves as a 68 series MPU enable clock input pin.  
WR  
(R/W)  
I
When the 80 series MPU is connected.  
A pin for connection of the WR signal of the 80 series MPU.  
Signals on the data bus are latched at the leading edge of the  
WR signal.  
1
Serves as a read/write control signal input pin when the 68 series  
MPU is connected.  
R/W = HIGH : Read  
R/W = LOW : Write  
C86  
P/S  
I
I
A MPU interface switching pin.  
C86 = HIGH : 68 series MPU interface  
C86 = LOW : 80 series MPU interface  
1
1
Parallel data input/serial data input select pin  
P/S = HIGH : Parallel data input  
P/S = LOW : Serial data input  
The following Table shows the summary:  
P/S Data/Command  
Data  
Read/Write Serial clock  
HIGH  
LOW  
A0  
A0  
D0 to D7  
SI (D7)  
RD, WR  
Write only  
SCL (D6)  
When P/S = LOW, D0 to D5 are high impedance.  
D0 to D5 can be HIGH, LOW or open.  
RD(E) and WR(R/W) are locked to HIGH or LOW.  
The serial data input does not allow the RAM display data to be read.  
8
EPSON  
Rev. 2.1