Epson Research and Development
Page 87
Vancouver Design Center
7.5.3 Single Color 4-Bit Panel Timing
VNDP
VDP
FPFRAME
FPLINE
DRDY (MOD)
LINE1
LINE2
LINE3
LINE4
LINE479 LINE480
LINE1
LINE2
FPDAT[7:4]
FPLINE
DRDY (MOD)
HDP
HNDP
FPSHIFT
1-R1 1-G2 1-B3
1-B319
FPDAT7
FPDAT6
FPDAT5
FPDAT4
1-R320
1-G320
1-B320
1-G1 1-B2
1-R4
1-G4
1-B1
1-R2
1-R3
1-G3 1-B4
* Diagram drawn with 2 FPLINE vertical blank period
Example timing for a 640x480 panel
Figure 7-26: Single Color 4-Bit Panel Timing
VDP
VNDP
HDP
= Vertical Display Period
= (REG[039h] bits [1:0], REG[038h] bits [7:0]) + 1
= (REG[03Ah] bits [5:0]) + 1
= ((REG[032h] bits [6:0]) + 1) × 8 Ts
= ((REG[034h] bits [4:0]) + 1) × 8 Ts
= Vertical Non-Display Period
= Horizontal Display Period
= Horizontal Non-Display Period
HNDP
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
EPSON [ EPSON COMPANY ]
