Epson Research and Development
Page 63
Vancouver Design Center
Table 7-8: PC Card Timing
3.0V
5.0V
Symbol
Parameter
Min
Max
Min
Max Units
fCLK
TCLK
t2
Clock frequency
50
50
MHz
ns
Clock period
1/fCLK
1/fCLK
Clock pulse width high
Clock pulse width low
6
6
6
6
ns
t3
ns
A[20:1], M/R# setup to first CLK where CE1# = 0 or CE2# = 0 and either
OE# = 0 or WE# = 0
t4
4
3
ns
t5
t6
t7
t8
A[20:1], M/R# hold from rising edge of either OE# or WE#
CS# hold from rising edge of either OE# or WE#
0
0
2
3
0
0
2
2
ns
ns
ns
ns
Falling edge of either OE# or WE# to WAIT# driven low
Rising edge of either OE# or WE# to WAIT# tri-state
21
14
9
9
D[15:0] setup to third CLK where CE1# = 0, CE2# = 0 and WE# = 0
(write cycle)
t9
0
0
ns
t10
t11
t12
t13
D[15:0] hold (write cycle)
0
10
0
0
8
0
5
ns
ns
ns
ns
Falling edge OE# to D[15:0] driven (read cycle)
D[15:0] setup to rising edge WAIT# (read cycle)
Rising edge of OE# to D[15:0] tri-state (read cycle)
7
34
17
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
EPSON [ EPSON COMPANY ]
