Page 18
Epson Research and Development
Vancouver Design Center
4.3 S1D13506 Hardware Configuration
The S1D13506 latches MD15 through MD0 to allow selection of the bus mode and other
configuration data on the rising edge of RESET#. For details on configuration, refer to the
S1D13506 Hardware Functional Specification, document number X25B-A-001-xx.
The following table shows those configuration settings important to the MPC821 host bus
interface.
Table 4-2: Summary of Power-On/Reset Options
value on this pin at rising edge of RESET# is used to configure: (1/0)
S1D13506
Pin Name
1
110 = PowerPC host bus interface selected
Little Endian
0
MD[3:1]
MD4
Big Endian
MD5
Wait# signal is active high
Wait# signal is active low
Configure SUSPEND# pin as Hardware Suspend
Enable
MD9
Reserved
MD11
MD12
Alternate Host Bus Interface Selected
BUSCLK input divided by two
Primary Host Bus Interface Selected
BUSCLK input not divided
MD15
WAIT# is floating if S1D13506 is not selected
WAIT# is always driven
= required settings for MPC821 support.
4.4 Register/Memory Mapping
The DRAM on the MPC821 ADS board extends from address 0 through 3F FFFFh, so the
S1D13506 is addressed starting at 40 0000h. A total of 4M bytes of address space is used,
where the lower 2M bytes is reserved for the S1D13506 on-chip registers and the upper 2M
bytes is used to access the S1D13506 display buffer.
S1D13506
X25B-G-008-03
Interfacing to the Motorola MPC821 Microprocessor
Issue Date: 01/02/08
EPSON [ EPSON COMPANY ]
