Page 20
Epson Research and Development
Vancouver Design Center
4.6 Test Software
The test software is very simple. It configures chip select 4 (CS4) on the MPC821 to map
the S1D13506 to an unused 4M byte block of address space. Next, it loads the appropriate
values into the option register for CS4 and writes the value 0 to the S1D13506 register
REG[001h] to enable full S1D13506 memory/register decoding. Lastly, the software runs
a tight loop that reads the S1D13506 Revision Code Register REG[000h]. This allows
monitoring of the bus timing on a logic analyzer.
The following source code was entered into the memory of the MPC821ADS using the
line-by-line assembler in MPC8BUG (the debugger provided with the ADS board). Once
the program was executed on the ADS, a logic analyzer was used to verify operation of the
interface hardware.
It is important to note that when the MPC821 comes out of reset, the on-chip caches and
MMU are disabled. If the data cache is enabled, then the MMU must be set so that the
S1D13506 memory block is tagged as non-cacheable. This ensures the MPC821 does not
attempt to cache any data read from, or written to, the S1D13506 or its display buffer.
BR4
OR4
MemStart
DisableReg
RevCodeReg
equ
equ
equ
equ
equ
$120
$124
$40
$1
; CS4 base register
; CS4 option register
; upper word of S1D13506 start address
; address of S1D13506 Disable Register
; address of Revision Code Register
$0
Start
mfspr
andis.
andis.
oris
ori
stw
andis.
oris
ori
r1,IMMR
r1,r1,$ffff
r2,r0,0
r2,r2,MemStart
r2,r2,$0801
r2,BR4(r1)
r2,r0,0
r2,r2,$ffc0
r2,r2,$0608
; get base address of internal registers
; clear lower 16 bits to 0
; clear r2
; write base address
; port size 16 bits; select GPCM; enable
; write value to base register
; clear r2
; address mask – use upper 10 bits
; normal CS negation; delay CS ½ clock;
; no burst inhibit (13506 does this)
; write to option register
; clear r1
stw
r2,OR4(r1)
r1,r0,0
r1,r1,MemStart
r1,DisableReg(r1) ; write 0 to disable register
r0,RevCodeReg(r1) ; read revision code into r1
andis.
oris
stb
; point r1 to start of S1D13506 mem space
Loop
lbz
b
Loop
; branch forever
end
Note
MPC8BUG does not support comments or symbolic equates; these have been added for
clarity.
S1D13506
X25B-G-008-03
Interfacing to the Motorola MPC821 Microprocessor
Issue Date: 01/02/08
EPSON [ EPSON COMPANY ]
