Epson Research and Development
Page 13
Vancouver Design Center
4.2 S1D13506 Hardware Configuration
The S1D13506 latches MD15 through MD0 to allow selection of the bus mode and other
configuration data on the rising edge of RESET#. For details on configuration, refer to the
S1D13506 Hardware Functional Specification, document number X25B-A-001-xx.
The table below shows those configuration settings important to the NEC VR4102/VR4111
CPU interface.
Table 4-1: Summary of Power-On/Reset Options
value on this pin at rising edge of RESET# is used to configure:(1/0)
S1D13506
Pin Name
1
0
MD[3:1]
MD4
101 = MIPS/ISA Host Bus Interface
Little Endian
Big Endian
MD5
WAIT# is active high (1 = insert wait state)
WAIT# is active low (0 = insert wait state)
MD11
MD12
Alternate Host Bus Interface Selected
BUSCLK input divided by two
Primary Host Bus Interface Selected
BUSCLK input not divided
WAIT# is floating if S1D13506 is not selected
MD15
WAIT# is always driven
= configuration for NEC VR4102/VR4111 microprocessor
4.3 NEC V
R
4102/V 4111 Configuration
R
NEC VR4102/VR4111The NEC VR4102/VR4111 provides the internal address decoding
necessary to map an external LCD controller. Physical address 0A00 0000h to 0AFF
FFFFh (16M bytes) is reserved for an external LCD controller.
The S1D13506 supports up to 2M bytes of display buffer. The NEC VR4102/VR4111
address line A21 is used to select between the S1D13506 display buffer (A21=1) and
internal registers (A21=0).
The NEC VR4102/VR4111 has a 16-bit internal register named BCUCNTREG2 located at
address 0B00 0002h. It must be set to the value of 0001h to indicate that LCD controller
accesses using a non-inverting data bus.
Interfacing to the NEC VR4102/VR4111™ Microprocessors
S1D13506
Issue Date: 01/02/08
X25B-G-007-02
EPSON [ EPSON COMPANY ]
