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Epson Research and Development
Vancouver Design Center
4.6 Clock Synthesizer and Clock Options
For maximum flexibility, the S5U13506B00C implements a Cypress ICD2061A Clock
Generator. MCLKOUT from the clock chip is connected to CLKI of the S1D13506 and
VCLKOUT from the clock chip is connected to CLKI2 of the S1D13506. A 14.31818MHz
crystal (Y1) is connected to XTALIN of the clock chip and a 17.734475MHz oscillator
(U14) is connected to the FEATCLK input of the clock chip. The diagram below shows a
simplified representation of the clock synthesizer connections.
ICD2061A
Synthesizer reference
14.31818 MHz
XTALIN
CLKI
MCLKOUT
VCLKOUT
Feature clock for PAL TV
17.734475 MHz
CLKI2
FEATCLK
Figure 4-3: Symbolic Clock Synthesizer Connections
Upon power-up, CLKI (MCLKOUT) is 40MHz and CLKI2 (VCLKOUT) is configured to
25.175MHz.
4.6.1 Clock Programming
The S1D13506 utilities automatically program the clock generator. If manual programming
of the clock generator is required, refer to the source code for the S1D13506 utilities
available on the internet at www.eea.epson.com.
For further information on programming the clock generator, refer to the Cypress
ICD2061A specification.
Note
When CLKI and CLKI2 are programmed to multiples of each other (e.g. CLKI =
20MHz, CLKI2 = 40MHz), the clock output signals from the Cypress clock generator
may jitter. Refer to the Cypress ICD2061A specification for details.
To avoid this problem, set CLKI and CLKI2 to different frequencies and configure both
LCD PCLK and CRT/TV PCLK to use the same clock input (CLKI or CLKI2).Then use
the S1D13506 internal clock divides (LCD PCLK Divide Select REG[014h] bits 5-4,
CRT/TV PCLK Divide Select REG[018h] bits 5-4) to obtain the lower frequencies.
S1D13506
X25B-G-004-06
S5U13506B00C Evaluation Board User Manual
Issue Date: 01/02/06
EPSON [ EPSON COMPANY ]
