Page 64
Epson Research and Development
Vancouver Design Center
REG[103h] BitBLT Operation Register
BitBLT
Operation
Bit 3
BitBLT
Operation
Bit 2
BitBLT
Operation
Bit 1
BitBLT
Operation
Bit 0
n/a
n/a
n/a
n/a
The BitBLT Operation Register selects the BitBLT operation to be carried out based on the
following table:
Table 10-2: BitBLT Operation Selection
BitBLT Operation Bits [3:0]
Blit Operation
Write Blit with ROP
0000
0001
Read Blit
0010
Move Blit in positive direction with ROP
Move Blit in negative direction with ROP
Transparent Write Blit
0011
0100
0101
Transparent Move Blit in positive direction
Pattern Fill with ROP
0110
0111
Pattern Fill with transparency
Color Expansion
1000
1001
Color Expansion with transparency
Move Blit with Color Expansion
Move Blit with Color Expansion and transparency
Solid Fill
1010
1011
1100
Other combinations
Reserved
REG[104h] BitBLT Source Start Address Register 0
BitBLT BitBLT BitBLT BitBLT
Source Start Source Start Source Start Source Start Source Start Source Start Source Start Source Start
BitBLT
BitBLT
BitBLT
BitBLT
Address
Bit 7
Address
Bit 6
Address
Bit 5
Address
Bit 4
Address
Bit 3
Address
Bit 2
Address
Bit 1
Address
Bit 0
REG[105h] BitBLT Source Start Address Register 1
BitBLT BitBLT BitBLT BitBLT
BitBLT
BitBLT
BitBLT
BitBLT
Source Start Source Start Source Start Source Start Source Start Source Start Source Start Source Start
Address
Bit 15
Address
Bit 14
Address
Bit 13
Address
Bit 12
Address
Bit 11
Address
Bit 10
Address
Bit 9
Address
Bit 8
REG[106h] BitBLT Source Start Address Register 2
BitBLT
BitBLT
BitBLT
BitBLT
BitBLT
Source Start
Bit 18
Source Start Source Start
Address
Bit 20
Source Start Source Start
Address Bit
17
n/a
n/a
n/a
Address
Bit 19
Address
Bit 16
The BitBLT Source Start Address Registers form a 21-bit register that specifies the source
start address for the BitBLT operation selected by the BitBLT Operation Register
(REG[103h]).
S1D13506
X25B-G-003-03
Programming Notes and Examples
Issue Date: 01/02/06
EPSON [ EPSON COMPANY ]
