Epson Research and Development
Page 63
Vancouver Design Center
REG[101h] BitBLT Control Register 1
BitBLT Color
Format Select
n/a
n/a
n/a
Reserved
n/a
n/a
n/a
n/a
n/a
This bit is reserved and must be set to 0.
REG[101h] BitBLT Control Register 1
n/a n/a n/a
BitBLT Color
Format Select
Reserved
n/a
The BitBLT Color Format Select bit selects the color format that the BitBLT operation is
applied to. When this bit = 0, 8 bpp (256 color) format is selected. When this bit = 1, 16 bpp
(64K color) format is selected.
REG[102h] BitBLT ROP Code/Color Expansion Register
BitBLT ROP
BitBLT ROP
Code
BitBLT ROP
Code
BitBLT ROP
Code
n/a
n/a
n/a
n/a
Code
Bit 3
Bit 2
Bit 1
Bit 0
The BitBLT ROP Code/Color Expansion Register selects the Raster Operation (ROP) used
for the Write blit, Move blit, and Pattern fill. It is also used to specify the start bit position
for BitBLTs with color expansion. The following table summarizes the functionality of this
register.
Table 10-1: BitBLT ROP Code/Color Expansion Function Selection
BitBLT ROP Code
Bits [3:0]
0000
Boolean Function for Write
Boolean Function for
Start Bit Position for Color
Blit and Move Blit
Pattern Fill
Expansion
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
0 (Blackness)
0 (Blackness)
0001
~S . ~D or ~(S + D)
~P . ~D or ~(P + D)
0010
~S . D
~P . D
0011
~S
~P
0100
S . ~D
P . ~D
0101
~D
S ^ D
~D
P ^ D
0110
0111
~S + ~D or ~(S . D)
S . D
~P + ~D or ~(P . D)
P . D
1000
bit 0
bit 1
1001
~(S ^ D)
D
~(P ^ D)
D
1010
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
1011
~S + D
~P + D
1100
S
P
1101
S + ~D
P + ~D
1110
S + D
P + D
1111
1 (Whiteness)
1 (Whiteness)
S = Source, D = Destination, P = Pattern
Operators: ~ = NOT, . = Logical AND, + = Logical OR, ^ = Logical XOR
Programming Notes and Examples
Issue Date: 01/02/06
S1D13506
X25B-G-003-03
EPSON [ EPSON COMPANY ]
